Quantum Error Correction Codes for Noisy Intermediate-Scale Quantum Devices: Implementation Trade-offs of Surface Codes, Steane Codes, and Bacon-Shor Codes on Superconducting Qubit Architectures
Quantum error correction (QEC) is widely recognized as a prerequisite for fault-tolerant quantum computation, yet the overhead requirements of leading QEC codes -- in terms of physical-to-logical qubit ratios and gate operation counts -- exceed the capabilities of current Noisy Intermediate-Scale Quantum (NISQ) devices by orders of magnitude. This paper investigates the implementation trade-offs of three QEC code families -- Surface Codes, Steane Codes, and Bacon-Shor Codes -- on superconducting transmon qubit architectures representative of current IBM Quantum and Google Sycamore hardware generations. Using a hardware-calibrated noise model derived from publicly available device characterization data, we simulate QEC circuit performance across logical qubit distances 3 through 9, measuring logical error rate suppression, syndrome extraction circuit depth, connectivity requirements, and decoding latency. Surface codes achieve the best logical error rate suppression per physical qubit overhead at distance 5 (logical error rate 2.3x10-4 at 0.1% physical gate error rate), but require all-nearest-neighbor connectivity that strains current device topologies. Bacon-Shor codes demonstrate the lowest syndrome extraction circuit depth, making them favorable for architectures with limited two-qubit gate fidelity. We introduce a QEC Code Suitability Index (QCSI) that maps device connectivity, gate fidelity, and coherence time profiles to code family recommendations, and apply it across six current quantum hardware platforms.
